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Freescale Semiconductor Technical Data
MPC9239 Rev. 3, 08/2005
900 MHz Low Voltage LVPECL Clock Synthesizer
The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 3.125 MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * 3.125 MHz to 900 MHz synthesized clock output signal Differential LVPECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference input 3.3 V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 28 PLCC and 32 LQFP packaging 28-lead and 32-lead Pb-free package available SiGe Technology Ambient temperature range 0C to + 70C Pin and function compatible to the MC12439
MPC9239
900 MHz LOW VOLTAGE CLOCK SYNTHESIZER
FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02
EI SUFFIX 28-LEAD PLCC PACKAGE Pb-FREE PACKAGE CASE 776-02 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0 V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the fOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back up to its programmed frequency in four discrete increments.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
XTAL_IN XTAL_OUT fREF_EXT
XTAL 10 - 20 MHz
1 /2 0 Ref VCO /2
PLL 800 - 1800 MHz FB /0 TO /127 7-BIT M-DIVIDER /2
/1 /2 /4 /8
11 00 01 10
/16
1 OE 0
fOUT fOUT
VCC XTAL_SEL VCC P_LOAD S_LOAD LE P/S
TEST 2 N-LATCH 3 T-LATCH
TEST
9 M-LATCH
0 S_DATA S_CLOCK BITS 11-5 VCC
1 BITS 3-4
0
1 BITS 0-2
12-BIT SHIFT REGISTER
M[0:6] N[1:0] PWR_DOWN OE
Figure 1. MPC9239 Logic Diagram
XTAL_SEL
M[6]
M[5] 18
TEST
GND
S_CLOCK S_DATA S_LOAD VCC_PLL PWR_DOWN fREF_EXT XTAL_IN
2 6 2 7 2 8 1 2 3 4
25
24
23
22
21
20
GND
fOUT
VCC
fOUT
VCC
19
18 17 16
N[1] N[0] NC XTAL_SEL M[6] M[5] M[4]
24 GND TEST VCC VCC GND fOUT fOUT VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10 9 8 XTAL_IN
N[1]
N[0] 3
NC
MPC9239
15 14 13 12
MPC9239
5 XTAL_OUT
6 OE
7 P_LOAD
8 M[0]
9 M[1]
10 M[2]
11 M[3]
2
NC 4
5
6
7
S_CLOCK
S_DATA
PWR_DOWN
S_LOAD
VCC_PLL
VCC_PLL
Figure 2. MPC9239 28-Lead PLCC Pinout (Top View)
Figure 3. MPC9239 32-Lead LQFP Pinout (Top View)
MPC9239 2 Advanced Clock Drivers Devices Freescale Semiconductor
fREF_EXT
Table 1. Pin Configurations
Pin XTAL_IN, XTAL_OUT fREF_EXT fOUT, fOUT TEST XTAL_SEL PWR_DOWN Input Output Output Input Input 1 0 0 I/O Default Type Analog LVCMOS LVPECL LVCMOS LVCMOS LVCMOS Crystal oscillator interface. Alternative PLL reference input. Differential clock output. Test and device diagnosis output. PLL reference select input. Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD. Output enable (active high). The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the fOUT output. OE = L low stops fOUT in the logic low stat (fOUT = L, fOUT = H). Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). Do not connect. Function
S_LOAD
Input
0
LVCMOS
P_LOAD
Input
1
LVCMOS
S_DATA S_CLOCK M[0:6] N[1:0] OE
Input Input Input Input Input
0 0 1 1 1
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
GND VCC VCC_PLL NC
Supply Supply Supply
Ground VCC VCC
Table 2. Output Frequency Range and PLL Post-Divider N
PWR_DOWN 0 0 0 0 1 1 1 1 N 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 VCO Output Frequency Division 2 4 8 1 32 64 128 16 fOUT Frequency Range 200 - 450 MHz 100 - 225 MHz 50 - 112.5 MHz 400 - 900 MHz 12.5 - 28.125 MHz 6.25 - 14.0625 MHz 3.125 - 7.03125 MHz 25 - 56.25 MHz
MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 3
Table 3. Function Table
Input XTAL_SEL OE PWR_DOWN 0 fREF_EXT Outputs disabled. fOUT is stopped in the logic low state (fOUT = L, fOUT = H) Output divider / 1 1 XTAL interface Outputs enabled Output divider / 16
Table 4. General Specifications
Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Input Capacitance LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
JESD 51-6, 2S2P multilayer test board
JC
LQFP 32 Thermal Resistance Junction to Case
Table 5. Absolute Maximum Ratings(1)
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
MPC9239 4 Advanced Clock Drivers Devices Freescale Semiconductor
Table 6. DC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)
Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (fREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) VIH VIL IIN VOH VOL VOH VOL ICC_PLL ICC Input High Voltage Input Low Voltage Input Current(1)
(2)
2.0
VCC + 0.3 0.8 200
V V A
LVCMOS LVCMOS VIN = VCC or GND LVPECL LVPECL
Differential Clock Output fOUT Output Low
Output High Voltage(3) Voltage(3)
VCC-1.02 VCC-1.95 2.0
VCC-0.74 VCC-1.60
V V
Test and Diagnosis Output TEST Output High Voltage(3) Output Low Voltage(3) V 0.55 V IOH = -0.8 mA IOL = 0.8 mA VCC_PLL Pins All VCC Pins
Supply Current Maximum PLL Supply Current Maximum Supply Current 62 20 100 mA mA
1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 to VTT = VCC - 2 V. 3. The MPC9239 TEST output levels are compatible to the MC12429 output levels. The MPC9239 is capable of driving 25 loads.
Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0C to +70C)(1)
Symbol fXTAL fVCO fMAX Characteristics Crystal Interface Frequency Range VCO Frequency Range(2) N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) Min 10 800 400 300 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) N = 11 (/ 1) N = 00 (/ 2) N = 01 (/ 4) N = 10 (/ 8) 20 20 20 20 20 60 90 120 160 40 65 90 120 10 50 55 0.3 Typ Max 20 1800 900 450 225 112.5 10 Unit MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps ps ps ps ps ps ps ms 20% to 80% PWR_DOWN = 0 Condition
Output Frequency
fS_CLOCK tP,MIN DC tr, tf tS
Serial Interface Programming Clock Frequency(3) Minimum Pulse Width Output Duty Cycle Output Rise/Fall Time Setup Time (S_LOAD, P_LOAD)
tS tJIT(CC)
Hold Time Cycle-to-Cycle Jitter
tJIT(PER)
Period Jitter
tLOCK
Maximum PLL Lock Time
1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. Refer to the application section for more details.
MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 5
Table 8. MPC9239 Frequency Operating Range (in MHz)
M 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ... M[6:0] 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1260 1260 1280 ... 816 840 864 888 912 936 960 984 1008 1032 1056 1080 1104 1128 1152 1176 1200 1224 1248 1272 1296 1320 1344 1368 1392 1416 1440 1488 1512 1512 1536 ... 812 840 875 868 896 924 952 980 1008 1036 1064 1092 1120 1148 1176 1204 1232 1260 1288 1316 1344 1372 1400 1428 1456 1484 1512 1540 1568 1596 1624 1652 1680 1736 1764 1764 1792 ... 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 828 864 900 936 972 1008 1044 1080 1116 1152 1188 1224 1260 1296 1332 1368 1404 1440 1476 1512 1548 1584 1620 1656 1692 1728 1764 1800 VCO frequency for a crystal interface frequency of 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Output frequency for fXTAL = 16 MHz and for N = 1 2 4 8
MPC9239 6 Advanced Clock Drivers Devices Freescale Semiconductor
Programming the MPC9239 Programming the MPC9239 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL / 2) (M 4) / (N 2) or (2) fOUT = fXTAL M / N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: (3) MMIN = fVCO,MIN / (2 fXTAL) and (4) MMAX = fVCO,MAX / (2 fXTAL) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 16 M / N Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 10 MHz
N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 fOUT 8M 4M 2M 16M fOUT Range 200-450 MHz 100-225 MHz 50-112.5 MHz 400-900 MHz fOUT Step 8 MHz 4 MHz 2 MHz 16 MHz
is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the fOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1, and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9239 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents fOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1, and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL fOUT outputs are as jitterfree as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9239 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9239 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the fOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving fOUT directly gives the user more control on the test clocks sent through the clock tree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the fOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle.
Example Calculation for an 16 MHz Input Frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, fOUT = 8M, and M = fOUT / 8. Therefore, M = 384 / 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL / N Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal
MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 7
Table 10. Test and Debug Configuration for TEST
T[2:0] T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output 12-bit shift register out(1) Logic 1 fXTAL / 2 M-Counter out fOUT Logic 0 M-Counter out in PLL-bypass mode fOUT / 4
Table 11. Debug Configuration for PLL Bypass(1)
Output fOUT TEST S_CLOCK / N M-Counter out(2) Configuration
1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode. 2. Clocked out at the rate of S_CLOCK / (2 N)
1. Clocked out at the rate of S_CLOCK.
S_CLOCK S_DATA S_LOAD M[6:0] N[1:0] P_LOAD M, N T2 First Bit T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 Last Bit
Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC9239 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC9239 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9239. Figure 5 illustrates a typical power supply filter scheme. The MPC9239 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9239 pin of the MPC9239. From the data sheet, the VCC_PLLcurrent (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 to meet the MPC9239 8 Advanced Clock Drivers Devices Freescale Semiconductor voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 ).
VCC RF = 10-15 CF = 22 F C2 VCC_PLL MPC9239 VCC C1, C2 = 0.01...0.1 F C1
Figure 5. VCC_PLL Power Supply Filter
Layout Recommendations The MPC9239 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC9239. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC9239 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on--board oscillator. Although the MPC9239 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
C1 C1
Using the On-Board Crystal Oscillator The MPC9239 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC9239 as possible to avoid any board level parasitics. To facilitate colocation surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the XTAL terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9239 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the MPC9239. Table 12. Recommended Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance* 75 ppm at 25C 150 pm 0 to 70C 0 to 70C 5-7 pF 50 to 80 100 W 5ppm/Yr (First 3 Years)
1
CF
C2
XTAL
= VCC = GND = Via
* See accompanying text for series versus parallel resonant discussion.
Figure 6. PCB Board Layout Recommendation for the PLCC28 Package
MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 9
PACKAGE DIMENSIONS
B -NY BRK
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
D Z -L-M-
W
28 1
D
V
X
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D-D
A Z R C 0.007 (0.180)
M
0.007 (0.180)
M
T L-M T L-M
S
N
S
S
H
0.007 (0.180)
M
T L-M
S
N
S
N
S
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1
J
-TVIEW S
SEATING PLANE
K F 0.007 (0.180) VIEW S
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXISTS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DEMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASITC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MILLIMETERS MAX MAX MIN MIN 12.57 0.485 0.495 12.32 12.57 0.485 0.495 12.32 4.20 4.57 0.165 0.180 2.29 2.79 0.090 0.110 0.33 0.48 0.013 0.019 0.050 BSC 1.27 BSC 0.032 0.66 0.81 0.026 --0.020 --0.51 --0.025 --0.64 0.450 0.456 11.43 11.58 11.58 0.450 0.456 11.43 0.042 0.048 1.07 1.21 1.07 1.21 0.042 0.048 1.42 0.042 0.056 1.07 0.020 --0.50 --2 10 2 10 0.410 0.430 10.42 10.92 --1.02 --0.040
CASE 776-02 ISSUE D 28-LEAD PLCC PACKAGE
MPC9239 10 Advanced Clock Drivers Devices Freescale Semiconductor
PACKAGE DIMENSIONS
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CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE
MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 11
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE
MPC9239 12 Advanced Clock Drivers Devices Freescale Semiconductor
PACKAGE DIMENSIONS
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CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE
MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 13
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MPC9239 Rev. 3 08/2005

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